? 2003 fairchild semiconductor corporation ds011614 www.fairchildsemi.com june 1993 revised september 2003 74lvx273 low voltage octal d-type flip-flop 74lvx273 low voltage octal d-type flip-flop general description the lvx273 has eight edge-triggered d-type flip-flops with individual d inputs and q outputs. the common buffered clock (cp) and master reset (mr ) input load and reset (clear) all flip-flops simultaneously. the register is fully edge-triggered. the state of each d input, one setup time before the low-to-high clock transi- tion, is transferred to the corresponding flip-flop?s q output. all outputs will be forced low independently of clock or data inputs by a low voltage level on the mr input. the device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. the inputs tolerate up to 7v allowing interface of 5v systems to 3v systems. features input voltage translation from 5v to 3v ideal for low power/low noise 3.3v applications guaranteed simultaneous switching noise level and dynamic threshold performance ordering code: devices also available in tape and reel. specify by appending letter suffix ? x ? to the ordering code. logic symbols ieee/iec pin descriptions connection diagram truth table h = high voltage level x = immaterial l = low voltage level = low-to-high transition order number package number package description 74lvx273m m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvx273sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lvx273mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description d 0 ? d 7 data inputs mr master reset cp clock pulse input q 0 ? q 7 data outputs operating mode inputs outputs mr cp d n q n reset (clear) l x x l load '1' h hh load '0' h ll
www.fairchildsemi.com 2 74lvx273 logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays.
3 www.fairchildsemi.com 74lvx273 absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: unused inputs must be held high or low. they may not float. dc electrical characteristics noise characteristics (note 3) note 3: input t r = t f = 3ns supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma dc input voltage (v i ) ? 0.5v to 7v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 25 ma dc v cc or ground current (i cc or i gnd ) 75 ma storage temperature (t stg ) ? 65 c to + 150 c power dissipation 180 mw supply voltage (v cc ) 2.0v to 3.6v input voltage (v i ) 0v to 5.5v output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c input rise and fall time ( ? t/ ? v) 0 ns/v to 100 ns/v symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions min typ max min max v ih high level 2.0 1.5 1.5 input voltage 3.0 2.0 2.0 v 3.6 2.4 2.4 v il low level 2.0 0.5 0.5 input voltage 3.0 0.8 0.8 v 3.6 0.8 0.8 v oh high level 2.0 1.9 2.0 1.9 v in = v ih or v il i oh = ? 50 a output voltage 3.0 2.9 3.0 2.9 v i oh = ? 50 a 3.0 2.58 2.48 i oh = ? 4 ma v ol low level 2.0 0.0 0.1 0.1 v in = v ih or v il i ol = 50 a output voltage 3.0 0.0 0.1 0.1 v i ol = 50 a 3.0 0.36 0.44 i ol = 4 ma i oz 3-state output 3.6 0.25 2.5 av in = v ih or v il off-state current v out = v cc or gnd i in input leakage current 3.6 0.1 1.0 av in = 5.5v or gnd i cc quiescent supply current 3.6 4.0 40.0 av in = v cc or gnd symbol parameter v cc t a = 25 c units c l (pf) (v) typ limit v olp quiet output maximum dynamic v ol 3.3 0.5 0.8 v 50 v olv quiet output minimum dynamic v ol 3.3 ? 0.5 ? 0.8 v 50 v ihd minimum high level dynamic input voltage 3.3 2.0 v 50 v ild maximum low level dynamic input voltage 3.3 0.8 v 50
www.fairchildsemi.com 4 74lvx273 ac electrical characteristics note 4: parameter guaranteed by design. t oslh = |t plhm ? t plhn |, t oshl = |t phlm ? t phln | capacitance note 5: c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units c l (pf) (v) min typ max min max t plh propagation 2.7 9.0 16.9 1.0 20.5 ns 15 t phl delay time 11.5 20.0 1.0 24.0 50 cp to q n 3.3 0.3 7.1 11.0 1.0 13.0 15 9.6 14.5 1.0 16.5 50 t phl propagation delay 2.7 9.3 17.8 1.0 20.5 ns 15 mr to q n 11.8 21.1 1.0 24.0 50 3.3 0.3 7.3 11.5 1.0 13.5 15 9.8 15.0 1.0 17.0 50 t s setup time 2.7 8.0 9.5 ns d n to cp 3.3 0.3 5.5 6.5 t h hold time 2.7 1.0 1.0 ns d n to cp 3.3 0.3 1.0 1.0 t rec removal time 2.7 4.0 4.0 ns mr to cp 3.3 0.3 2.5 2.5 t w clock pulse 2.7 8.0 9.5 ns width 3.3 0.3 5.5 6.5 t w mr pulse 2.7 7.5 8.5 ns width 3.3 0.3 5.0 6.0 f max maximum 2.7 55 110 45 mhz 15 clock 45 60 40 50 frequency 3.3 0.3 95 150 80 15 60 90 50 50 t oslh output to output 2.7 1.5 1.5 ns 50 t oshl skew (note 4) 3.3 1.5 1.5 symbol parameter t a = + 25 ct a = ? 40 c to + 85 c units min typ max min max c in input capacitance 4 10 10 pf c out output capacitance 6 pf c pd power dissipation 31 pf capacitance (note 5)
5 www.fairchildsemi.com 74lvx273 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 6 74lvx273 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
7 www.fairchildsemi.com 74lvx273 low voltage octal d-type flip-flop physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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